US 12,106,790 B2
Magnetoresistive memory device and method of operating same using ferroelectric-controlled exchange coupling
Alan Kalitsov, San Jose, CA (US); Derek Stewart, Livermore, CA (US); Ananth Kaushik, Santa Clara, CA (US); and Gerardo Bertero, Fremont, CA (US)
Assigned to SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed by SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed on Mar. 24, 2022, as Appl. No. 17/656,306.
Prior Publication US 2023/0307027 A1, Sep. 28, 2023
Int. Cl. G11C 11/16 (2006.01); G01R 33/09 (2006.01); H01F 10/32 (2006.01); H10B 61/00 (2023.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01); H10N 50/85 (2023.01)
CPC G11C 11/161 (2013.01) [G01R 33/093 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); H01F 10/3286 (2013.01); H10B 61/00 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02); H10N 50/85 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A memory device comprising at least one three-terminal magnetoresistive memory cell which comprises:
a first terminal electrode;
a second terminal electrode;
a middle electrode located between the first terminal electrode and the second terminal electrode;
a magnetoresistive layer stack comprising a reference layer, a free layer and a nonmagnetic spacer layer located between the reference layer and the free layer, wherein the magnetoresistive layer stack is located between the first terminal electrode and the middle electrode;
a ferroelectric material layer located between the middle electrode and the second terminal electrode; and a perpendicular magnetic anisotropy (PMA) layer located between the ferroelectric material layer and the magnetoresistive layer stack.