a frame buffer configured to sequentially store a plurality of frame data received from a host processor, each of the plurality of frame data including a plurality of data slices;

a plurality of image processing circuits configured to perform image signal processing operations, respectively, on ones of the plurality of data slices that are included in a respective one of the plurality of frame data and which are sequentially retrieved from the frame buffer; and

an image processing controller configured to bypass at least one of the plurality of image processing circuits by applying a bypass control signal to the plurality of image processing circuits based on a first plurality of data slices included in a first one of the plurality of frame data and a second plurality of data slices included in a second one of the plurality of frame data,

wherein the first one of the plurality of frame data is stored in the frame buffer and the second one of the plurality of frame data is received after the first one of the plurality of frame data from the host processor, and

wherein the second one of the plurality of data slices corresponds to the first one of the plurality of data slices,

wherein the image processing controller includes:

a comparison circuit configured to generate a comparison signal indicating whether the first one of the first plurality of data slices is equal to the second one of the second plurality of data slices based on first values included in the first one of the plurality of data slices and second values included in the second one of the plurality of data slices; and

a control signal generator configured to, based on the comparison signal and image processing circuit information from the plurality of image processing circuits, generate an image processing circuit control signal including the bypass control signal, the image processing circuit control signal being used to control each of the plurality of image processing circuits, the image processing circuit information representing target image types of the image signal processing operations performed by the plurality of image processing circuits.