US 12,106,729 B2
Display device and electronic device
Susumu Kawashima, Kanagawa (JP); and Naoto Kusumoto, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Apr. 10, 2023, as Appl. No. 18/132,554.
Application 18/132,554 is a continuation of application No. 17/536,341, filed on Nov. 29, 2021, granted, now 11,626,082.
Application 17/536,341 is a continuation of application No. 16/962,570, granted, now 11,355,082, issued on Nov. 12, 2020, previously published as PCT/IB2019/050507, filed on Jan. 22, 2019.
Claims priority of application No. 2018-016572 (JP), filed on Feb. 1, 2018; and application No. 2018-020926 (JP), filed on Feb. 8, 2018.
Prior Publication US 2023/0335075 A1, Oct. 19, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/36 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G09G 3/3225 (2016.01); G09G 3/3266 (2016.01); G09G 3/3275 (2016.01); G09G 3/34 (2006.01); H01L 27/12 (2006.01); H01L 29/24 (2006.01); H01L 29/786 (2006.01); H04N 23/57 (2023.01); H10K 59/121 (2023.01); H10K 59/131 (2023.01); H10K 59/65 (2023.01)
CPC G09G 3/3688 (2013.01) [G02F 1/136213 (2013.01); G02F 1/13624 (2013.01); G02F 1/1368 (2013.01); G09G 3/3225 (2013.01); G09G 3/3266 (2013.01); G09G 3/3275 (2013.01); G09G 3/3413 (2013.01); G09G 3/3677 (2013.01); H01L 27/1225 (2013.01); H01L 27/124 (2013.01); H01L 27/1255 (2013.01); H01L 29/24 (2013.01); H01L 29/7869 (2013.01); H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); H10K 59/131 (2023.02); H10K 59/65 (2023.02); G09G 2300/0426 (2013.01); G09G 2300/0439 (2013.01); G09G 2300/0809 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/0252 (2013.01); G09G 2330/021 (2013.01); H04N 23/57 (2023.01)] 9 Claims
OG exemplary drawing
 
1. A method of driving a display device comprising the steps of:
supplying first data to a first wiring from a circuit;
making the first wiring floating to hold the first data;
performing first writing of the first data to a first pixel in a period during which the first data is supplied to the first wiring;
performing second writing of the first data to the first pixel in a period during which the first data is held to the first wiring; and
performing addition of the first data after the second writing.