US 12,106,722 B2
Display substrate and manufacturing method therefor, and display apparatus
Haigang Qing, Beijing (CN); Yunsheng Xiao, Beijing (CN); and Quanyong Gu, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 18/272,814
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Dec. 22, 2021, PCT No. PCT/CN2021/140561
§ 371(c)(1), (2) Date Jul. 18, 2023,
PCT Pub. No. WO2023/115400, PCT Pub. Date Jun. 29, 2023.
Prior Publication US 2024/0087536 A1, Mar. 14, 2024
Int. Cl. G09G 3/3266 (2016.01); G09G 3/32 (2016.01); G11C 19/28 (2006.01)
CPC G09G 3/3266 (2013.01) [G09G 3/32 (2013.01); G11C 19/28 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A display substrate, comprising a display region and a non-display region, wherein the non-display region is provided with a gate drive circuit, and the gate drive circuit comprises a plurality of cascaded shift register units, which comprise an input circuit, a first control circuit, a second control circuit, and an output circuit;
wherein the input circuit is electrically connected with a first node, and the output circuit is electrically connected with a second node;
the first control circuit is electrically connected to the first node, the second node, and a third node, and is configured to control a voltage of the second node under control of the first node and the third node;
the second control circuit is electrically connected with the first node and the third node, and is configured to control a voltage of the third node under control of the first node; and
the first control circuit is located between the input circuit and the output circuit in a first direction, and the first control circuit is arranged along the first direction, and the second control circuit is adjacent to the first control circuit in a second direction, wherein the first direction intersects with the second direction,
wherein the first control circuit comprises a second transistor and a third transistor;
wherein active layers of the second transistor and the third transistor are of an integral structure and extend along the first direction;
wherein the second control circuit at least comprises a seventh transistor;
wherein control electrodes of the second transistor and the seventh transistor are of an integral structure and extend along the second direction;
wherein active layers of the second transistor and the seventh transistor are of an integral structure and form a U shape, and an opening of the U shape faces the input circuit.