| CPC G09G 3/32 (2013.01) [G09G 2310/0267 (2013.01); G09G 2310/0275 (2013.01)] | 20 Claims |
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1. An inverter circuit comprising:
an output transistor connected between a first voltage line and an output terminal outputting a second start signal, and including a gate electrode connected to an input terminal receiving a first start signal;
a first switching transistor connected between the first voltage line and the output terminal, and including a gate electrode connected to a first switching line receiving a first switching signal;
a second switching transistor connected between the output terminal and a first node, and including a gate electrode connected to a second switching line receiving a second switching signal; and
a discharge circuit that discharges the first node to a first bias clock signal in response to the first start signal, the first bias clock signal, and a second bias clock signal.
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9. A scan driving circuit comprising:
an inverter circuit that outputs a second start signal in response to a first start signal, a first switching signal, a second switching signal, a first bias clock signal, and a second bias clock signal;
a first scan driver that outputs first scan signals in response to the first start signal, a first clock signal, and a second clock signal; and
a second scan driver that outputs second scan signals in response to the second start signal, the first bias clock signal, and the second bias clock signal, and
wherein the inverter circuit includes:
an output transistor connected between a first voltage line and an output terminal outputting the second start signal, and including a gate electrode connected to an input terminal receiving the first start signal;
a first switching transistor connected between the first voltage line and the output terminal, and including a gate electrode connected to a first switching line receiving the first switching signal;
a second switching transistor connected between the output terminal and a first node, and including a gate electrode connected to a second switching line receiving the second switching signal; and
a discharge circuit that discharges the first node to the first bias clock signal in response to the first start signal, the first bias clock signal, and the second bias clock signal.
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16. A display device comprising:
a display panel including a pixel;
a scan driving circuit that provides a first scan signal and a second scan signal to the pixel;
a data driving circuit that provides a data signal to the pixel; and
a driving controller that provides a first start signal, a first switching signal, a second switching signal, a first bias clock signal, and a second bias clock signal to the scan driving circuit, wherein
the scan driving circuit includes:
an inverter circuit that outputs a second start signal in response to the first start signal, the first switching signal, the second switching signal, the first bias clock signal, and the second bias clock signal;
a first scan driver that outputs the first scan signal in response to the first start signal, a first clock signal, and a second clock signal; and
a second scan driver that outputs the second scan signal in response to the second start signal, the first bias clock signal, and the second bias clock signal,
the inverter circuit outputs the second start signal of a certain voltage level in response to the first switching signal of a first level and the second switching signal of a second level during a power-on period and a power-off period, and
the inverter circuit outputs the second start signal that is a complementary signal of the first start signal during an operation period.
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