CPC G06V 40/1318 (2022.01) [G09G 3/3233 (2013.01); H10K 39/34 (2023.02); H10K 59/131 (2023.02); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0202 (2013.01); G09G 2310/08 (2013.01); G09G 2354/00 (2013.01); G09G 2360/14 (2013.01)] | 17 Claims |
1. A display device, comprising:
scan lines including a first scan line and a second scan line which are adjacent to each other;
pixels connected to the scan lines;
photo sensors connected to at least some of the scan lines, the photo sensors comprising a first photo sensor connected to the first scan line and a readout line, and a second photo sensor connected to the second scan line and the readout line;
a scan driver configured to provide scan signals to the scan lines; and
a readout circuit configured to receive, through the readout line, detection signals which are outputted from the photo sensors in response to the scan signals,
wherein, while the scan signals are provided to the first and second scan lines, the readout circuit samples a detection signal of one of the first photo sensor and the second photo sensor without sampling a detection signal of the other one of the first photo sensor and the second photo sensor,
wherein the readout circuit comprises:
an integrating circuit configured to integrate a signal flowing through the readout line;
a first sampling circuit configured to sample an output of the integrating circuit and generate a first sampling signal;
a second sampling circuit configured to sample the output of the integrating circuit and generate a second sampling signal; and
an analog-digital converter configured to output a digital value corresponding to a difference between the first sampling signal and the second sampling signal,
wherein, during a first period in which a scan signal is applied to the first scan line, the integrating circuit and the readout line are reset,
wherein, in a second period between the first period and a third period in which a scan signal is applied to the second scan line, the first sampling circuit generates the first sampling signal, and
wherein, in the third period, the second sampling circuit generates the second sampling signal.
|