| CPC G06N 3/065 (2023.01) [G06N 3/049 (2013.01); G11C 16/0425 (2013.01); G11C 16/0458 (2013.01); H01L 29/42324 (2013.01); H01L 29/42328 (2013.01); H01L 29/42344 (2013.01)] | 14 Claims |
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1. A Vector-by-Matrix Multiplication (VMM) circuit to implement larger neural networks, comprising:
first cells of field effect transistors (FETs), each of the first cells comprising a first FET and a second FET;
second cells of FETs each connected to one of the first cells, each of the second cells comprising a third FET and a fourth FET, and each of the FETs comprising:
a source (S), a drain (D), and a channel between the source and the drain;
a first gate disposed over a first portion of the channel and insulated from the first portion of the channel, the first gate controlling a first conductivity of the first portion in response to a first voltage applied to the first gate;
a second gate comprising a floating gate disposed over a second portion of the channel, the floating gate controlling a second conductivity of the second portion in response to an amount of charge (electrons or holes) stored on the floating gate;
a third gate comprising a gate coupled to the floating gate so as to control the amount of charge transferred to the floating gate during programming;
a first line electrically connecting the first gate in the first FET and the first gate in the third FET;
a second line electrically connecting the first gate in the second FET and the first gate in the fourth FET;
a third line electrically connecting the third gate in the first FET and the third gate in the third FET;
a fourth line electrically connecting the third gate in the second FET and the third gate in the fourth FET;
a fifth line electrically connecting the sources of the first and second FETs with the sources of the third and fourth FETs when the FETs are n-type FETs, or electrically connecting the drains of the first and second FETs with the drains of the third and fourth FETs when the FETs are p-type FETs;
a sixth line electrically connecting the drains of the third and fourth FETs when the FETs are n-type FETs, or electrically connecting the sources of the third and fourth FETs when the FETs are p-type FETs;
a first pass gate connecting the third gate in the first FET to the drain in the first FET when the FETs are n-type FETs or connecting the third gate in the first FET to the source in the first FET when the FETs are p-type FETs;
a second pass gate connecting the third gate in the second FET to the drain in the second FET when the FETs are n-type FETs or connecting the third gate in the second FET to the source in the second FET when the FETs are p-type FETs; and wherein:
the input current to the first FET is inputted to the drain of the first FET when the FETs are n-type FETs or the input current to the first FET is inputted to the source of the first FET when the FETs are p-type FETs;
the input current to the second FET is inputted to the drain of the second FET when the FETs are n-type FETs or the input current to the second FET is inputted to the source of the second FET when the FETs are p-type FETs;
the output current from the third FET is a dot product multiplication of the input current to the first FET and a weight determined by the amount of charge stored on the floating gates of the first FET and the third FET;
the output current from the fourth FET is a dot product multiplication of the input current to the second FET and a weight determined by the amount of charge stored on the floating gates of the second FET and the fourth FET; and
the FETs are operated in a subthreshold regime.
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