| CPC G06N 3/04 (2013.01) [G06F 9/3806 (2013.01); G06F 13/1657 (2013.01); G06F 13/1673 (2013.01); G06F 13/4022 (2013.01); G06N 3/063 (2013.01); G06T 7/11 (2017.01); G06T 2207/20084 (2013.01)] | 31 Claims |
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1. A convolutional accelerator framework (CAF), comprising:
a plurality of processing circuits including one or more convolution accelerators;
a reconfigurable hardware buffer configurable to store data of a variable number of input data channels, the reconfigurable hardware buffer having:
a memory including an input buffer memory, a mirror buffer and a random access memory (RAM); and
control circuitry; and
a stream switch coupled to the plurality of processing circuits and to the reconfigurable hardware buffer, wherein, in operation,
a number of the variable number of input data channels is associated with an execution epoch;
the stream switch streams data of the variable number of input data channels between processing circuits of the plurality of processing circuits and the reconfigurable hardware buffer during processing of the execution epoch;
the control circuity of the reconfigurable hardware buffer configures the memory to store data of the variable number of input data channels during processing of the execution epoch, the configuring including allocating a portion of the memory to each of the variable number of input data channels; and
the allocating a portion of the memory to an input data channel of the variable number of input data channels includes determining an input buffer of the input buffer memory to allocate to the input data channel, and determining a size of subRAM of the RAM to allocate to the input data channel.
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