	US 12,106,114 B2
	Microprocessor with shared read and write buses and instruction issuance to multiple register sets in accordance with a time counter
Thang Minh Tran, Tustin, CA (US)
Assigned to Simplex Micro, Inc., Austin, TX (US)
Filed by Simplex Micro, Inc., San Jose, CA (US)
Filed on Apr. 29, 2022, as Appl. No. 17/733,728.
Prior Publication US 2023/0350680 A1, Nov. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01)

CPC G06F 9/3836 (2013.01) [G06F 9/3838 (2013.01); G06F 9/384 (2013.01); G06F 9/3885 (2013.01); G06F 9/3012 (2013.01)]

23 Claims

1. A processor comprising:

a time counter storing a time count representing a current time of the processor, wherein the time count is incremented periodically;

a register file comprising a plurality of registers organized into at least two register sets, each of the register sets comprising a subset of the plurality of registers and wherein each of the register sets are of different sizes;

an instruction issue unit coupled to the time counter for receiving a first instruction and a second instruction, and issuing the first instruction with a first preset execution time based on the time count if the registers referenced by the first instruction are in a first register set, and issuing the second instruction with a second preset execution time based on the time count if the registers referenced by the second instruction are in a second register set;

a first execution queue coupled to the time counter and the instruction issue unit to receive the first instruction from the instruction issue unit, and dispatch the first instruction to a first functional unit when the first preset execution time corresponds to the time count;

a second execution queue coupled to the time counter and the instruction issue unit to receive the second instruction from the instruction issue unit, and dispatch the second instruction to a second functional unit when the second preset execution time corresponds to the time count;

a plurality of sets of read and write buses each set of read and write buses separately coupled to a corresponding set of functional units and a corresponding one of the at least two register sets;

wherein the read and write buses independently transport data between the corresponding one of the at least two register sets and the corresponding set of functional units;

a plurality of shared read and write buses coupled to the register sets of the register file;

and one or more shared functional units wherein the shared read and write buses transport data between the register sets of the register file and the one or more shared functional units.