a memory comprising a memory bank including memory cells;

a processor in memory (PIM) circuit configured to process an operation using host data provided by a host or read data read from the memory bank, the PIM circuit including an instruction memory storing a plurality of instructions; and

control logic configured to decode a command and an address received from the host to generate a decoding result and cause the memory device to enter one of a memory operation mode and an operation processing mode based on the decoding result,

wherein the control logic is further configured to perform a control operation so that a memory operation is performed on the memory bank, when a bit value of at least one bit of the address belongs to a first range for the memory device to cause the memory device to enter the memory operation mode, and

wherein the control logic is further configured to perform a control operation so that the PIM circuit reads an instruction from the instruction memory, reads an operand from an operand position in the memory bank indicated by a part of the address different from the at least one bit, and performs a processing operation corresponding to the read instruction on the operand, when the bit value belongs to a second range different from the first range for the memory device to cause the memory device to enter the operation processing mode.