US 12,106,100 B2
Systems, methods, and apparatuses for matrix operations
Robert Valentine, Kiryat Tivon (IL); Mark J. Charney, Lexington, MA (US); Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US); Dan Baum, Haifa (IL); Zeev Sperber, Zichron Yackov (IL); Jesus Corbal, King City, OR (US); Bret L. Toll, Hillsboro, OR (US); Raanan Sade, Kibutz Sarid (IL); Igor Yanover, Yokneam Illit (IL); Yuri Gebil, Nahariya (IL); Rinat Rappoport, Haifa (IL); Stanislav Shwartsman, Haifa (IL); Menachem Adelman, Haifa (IL); and Simon Rubanovich, Haifa (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 16/487,421
Filed by Intel Corporation, Santa Clara, CA (US)
PCT Filed Jul. 1, 2017, PCT No. PCT/US2017/040546
§ 371(c)(1), (2) Date Aug. 20, 2019,
PCT Pub. No. WO2018/174935, PCT Pub. Date Sep. 27, 2018.
Claims priority of provisional application 62/473,732, filed on Mar. 20, 2017.
Prior Publication US 2020/0065352 A1, Feb. 27, 2020
Int. Cl. G06F 9/30 (2018.01); G06F 7/485 (2006.01); G06F 7/487 (2006.01); G06F 7/76 (2006.01); G06F 9/38 (2018.01); G06F 17/16 (2006.01)
CPC G06F 9/30036 (2013.01) [G06F 7/485 (2013.01); G06F 7/4876 (2013.01); G06F 7/762 (2013.01); G06F 9/3001 (2013.01); G06F 9/30032 (2013.01); G06F 9/30043 (2013.01); G06F 9/30109 (2013.01); G06F 9/30112 (2013.01); G06F 9/30134 (2013.01); G06F 9/30145 (2013.01); G06F 9/30149 (2013.01); G06F 9/3016 (2013.01); G06F 9/30185 (2013.01); G06F 9/30196 (2013.01); G06F 9/3818 (2013.01); G06F 9/3836 (2013.01); G06F 17/16 (2013.01); G06F 2212/454 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus comprising:
matrix operations circuitry to execute one or more decoded matrix operation instructions on data stored in two-dimensional data structures;
storage to store the two-dimensional data structures according to a to be loaded configuration, the to be loaded configuration to at least independently describe a number of rows and a number of columns per two-dimensional data structure, wherein the configuration is to be loaded in response to execution of a single matrix usage configuration instruction, wherein the single matrix usage configuration instruction is to not load data to be stored in a two-dimensional data structure; and
execution circuitry to execute the single matrix usage configuration instruction and to support a plurality of instructions to perform a computational operation after the execution of the single matrix usage configuration instruction.