US 12,106,099 B2
Execution or write mask generation for data selection in a multi-threaded, self-scheduling reconfigurable computing fabric
Tony M. Brewer, Plano, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 8, 2023, as Appl. No. 18/377,804.
Application 18/377,804 is a continuation of application No. 17/473,001, filed on Sep. 13, 2021, granted, now 11,782,710.
Application 17/473,001 is a continuation of application No. 16/996,055, filed on Aug. 18, 2020, granted, now 11,150,900, issued on Oct. 19, 2021.
Claims priority of provisional application 62/892,848, filed on Aug. 28, 2019.
Prior Publication US 2024/0045676 A1, Feb. 8, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01); G06F 9/448 (2018.01); G06F 15/78 (2006.01)
CPC G06F 9/30018 (2013.01) [G06F 9/30065 (2013.01); G06F 9/30087 (2013.01); G06F 9/30098 (2013.01); G06F 9/3824 (2013.01); G06F 9/4498 (2018.02); G06F 15/7867 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a packet communication network having a plurality of data transmission lines forming a data path;
a mesh communication network; and
a plurality of configurable circuits arranged in an array, each configurable circuit of the plurality of configurable circuits coupled to the packet communication network and to the mesh communication network, each configurable circuit of the plurality of configurable circuits comprising:
a configurable computation circuit configurable to perform a plurality of computations;
a memory circuit; and
an execution or write mask generator circuit comprising one or more registers and a state machine circuit, the execution or write mask generator circuit configured to generate an execution or write mask identifying valid bits or bytes transmitted on the data path or stored in the memory circuit for a current or next computation of the plurality of computations.