| CPC G06F 7/5443 (2013.01) [G06F 7/4876 (2013.01); G06F 2207/3884 (2013.01)] | 20 Claims |
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1. A floating point multiplier-accumulator (MAC) multiplying and accumulating N pairs of values, each pair of values comprising a respective input value and a corresponding coefficient value, the floating point MAC comprising:
a plurality N of MAC processors, each MAC processor receiving the respective input value and the corresponding coefficient value, each MAC processor comprising:
a sign processor configured to perform an exclusive OR operation on a sign bit of the respective input value and a sign bit of the corresponding coefficient value, the sign processor outputting a corresponding sign bit;
a mantissa processor configured to perform an integer multiplication of a mantissa of the respective input value and a mantissa of the corresponding coefficient value and outputting a fraction;
an exponent processor determining an exponent sum of an exponent of the respective input value and an exponent of the corresponding coefficient value, the exponent processor receiving a maximum exponent from a centralized find maximum exponent processor, the exponent processor modifying the maximum exponent and also outputting an exponent difference between the maximum exponent and the exponent sum;
a Pad, Complement, Shift (PCS) Processor receiving the fraction from the mantissa processor, the corresponding sign bit from the sign processor, and the exponent difference from the exponent processor, the PCS processor configured to pad the fraction by pre-pending and appending 0s to the fraction to generate a first value, thereafter performing a two's complement of the first value if the corresponding sign bit from the sign processor is negative and otherwise taking no action on the first value to generate a second value, the PCS processor configured to performing a shift operation on the second value by right shifting the second value by the exponent difference to generate a PCS output;
the centralized find maximum exponent processor receiving an exponent sum from each exponent processor of the MAC processors, the centralized find maximum exponent processor outputting a maximum exponent value corresponding to a maximum exponent sum;
a binary tree of adders summing N PCS output values to a single value;
a final stage normalizing the single value, generating a final stage mantissa by performing a 2s complement if the single value is negative, generating a final stage sign bit, and concatenating the final stage sign bit, final stage mantissa, and maximum exponent into a floating point MAC result.
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