| CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] | 26 Claims |
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1. A flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface, comprising:
a bus;
a specific buffer, coupled to the bus;
a processor, coupled to the bus and the specific buffer; and
a control logic circuit, coupled to the bus, the specific buffer, the processor, and coupled to the flash memory device through the specific communication interface, the control logic circuit comprises:
a comparison circuit; and
an input/output (I/O) circuit having a plurality of channel controllers corresponding to different channels of the flash memory device, a channel controller comprising an arbitrator and a plurality of queues corresponding to different chips of one channel;
wherein the processor issues and generates a command signal into the control logic circuit though the bus, and the command signal is buffered in a specific queue of a specific channel controller of the I/O circuit; the arbitrator controls the specific buffer storing a first transmission history information of the specific communication interface; the first transmission history information of the specific communication interface comprises at least one of: a data content and a data type of command information of the command signal when the command signal is selected by the arbitrator to output the command signal into the flash memory device, a data content and a data type of address information of the command signal when the command signal is selected by the arbitrator to output the command signal into the flash memory device, and a data type of a data input/output operation executed by the flash memory device.
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