| CPC G06F 3/0619 (2013.01) [G06F 3/0653 (2013.01); G06F 3/0679 (2013.01)] | 20 Claims |
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1. An apparatus, comprising:
a control circuit configured to connect to NAND strings that are connected to bit lines, each bit line connected to a plurality of NAND strings in a corresponding plurality of regions of a block, the control circuit configured to:
apply a read voltage in read operations directed to NAND strings of the plurality of regions of the block, subsequently, in response to a write erase cycle count of the block reaching a predetermined number of cycles, adjust the read voltage by a first predetermined amount for read operations directed to NAND strings of a first region of the block and adjust the read voltage by a second predetermined amount for read operations directed to NAND strings of a second region of the block, the first and second predetermined amounts based on respective locations of the first and second regions in the block.
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