| CPC G06F 3/061 (2013.01) [G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] | 20 Claims |
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1. A flash memory device to be used in a storage device and coupled to a flash memory controller of the storage device through a specific communication interface, comprising:
an input/output (I/O) control circuit, coupled to the flash memory controller through the specific communication interface;
a command register, coupled to the I/O control circuit, for buffering command information sent from the flash memory controller and transmitted through the I/O control circuit;
an address register, coupled to the I/O control circuit, for buffering address information sent from the flash memory controller and transmitted through the I/O control circuit;
a memory cell array, at least having a first plane and a second plane which is different from the first plane;
at least one address decoder, coupled to the memory cell array;
a status register, coupled to the I/O control circuit; and
a control circuit having a debug circuit, coupled to the logic control circuit, the memory cell array, the address register, the command register, and the status register, the debug circuit being arranged for automatically generating debug information of an access operation of an access command signal sent from the flash memory controller, transmitting the generated debug information into the status register, and controlling the status register transmitting the debug information from the flash memory device to the flash memory controller via the I/O control circuit and the specific communication interface;
wherein the access operation is a program operation, a cache program operation, or an erase operation; the debug information is associated with a simulated program failure, a simulated cache program failure, or a simulated erase failure, and the debug circuit does not control the memory cell array generating a program failure error, a cache program failure error, or an erase failure error.
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