processing circuitry;

a peripheral control hub;

a plurality of solid state drives coupled to the peripheral control hub, each respective solid state drive of the solid state drives comprising respective mass storage memory and a respective configuration context describing an internal context of the respective solid state drive; and,

a system memory to have allocated operating space for different application software programs executed by the processing circuitry, the system memory comprising program code outside of the solid state drives to be responsible for executing, by the processing circuitry, internal solid state drive operations within each respective solid state drive of the plurality of solid state drives,

wherein the system memory comprises additional program code having visibility to the configuration context of each of the plurality of solid state drives, the additional program code for load balancing the solid state drives by at least determining an internal command queue state of each respective solid state drive of the plurality of solid state drives based on the respective configuration context, and when an internal command queue state of a first solid state drive of the plurality of solid state drives is indicative of being less full than a second of the solid state drives, sending a storage request to the first solid state drive.