a first plurality of modular memory circuits, each comprising a plurality of thin-film storage transistors, formed above a planar surface of a first substrate;

a second plurality of modular memory circuits, comprising a plurality of thin-film storage transistors, formed above a planar surface of a second substrate, wherein (i) both the first and the second substrates each have formed therein through-silicon vias; (ii) the through-silicon vias of the first substrate are electrically connected with the first plurality of modular memory circuits and the through-silicon vias of the second substrate are electrically connected with the second plurality of modular memory circuits, and (iii) the first plurality of modular memory circuits and the second plurality of modular memory circuits are organized into a plurality of partitions, wherein each partition (a) comprises a plurality of modular memory circuits from both the first plurality of modular memory circuits and the second plurality of modular memory circuits, and (b) is assigned to a portion of an address space which does not overlap the portions of the address space assigned to other partitions; and

a memory controller circuit formed on a third substrate, wherein (i) the memory controller circuit comprises a plurality of memory channel controller each communicating data and control signals with one or more partitions through the through-silicon vias in the first substrate and through the through-silicon vias in the second substrate; and (ii) each memory channel controller comprises a first logic circuit for handling memory addresses, a second logic circuit for handling data stored or to be stored in the partition, and an arithmetic logic unit operating in conjunction with the first logical circuit and the second logic circuit.