CPC G06F 12/1045 (2013.01) [G06F 7/24 (2013.01); G06F 7/487 (2013.01); G06F 7/4876 (2013.01); G06F 7/49915 (2013.01); G06F 7/53 (2013.01); G06F 7/57 (2013.01); G06F 9/3001 (2013.01); G06F 9/30014 (2013.01); G06F 9/30021 (2013.01); G06F 9/30032 (2013.01); G06F 9/30036 (2013.01); G06F 9/30065 (2013.01); G06F 9/30072 (2013.01); G06F 9/30098 (2013.01); G06F 9/30112 (2013.01); G06F 9/30145 (2013.01); G06F 9/30149 (2013.01); G06F 9/3016 (2013.01); G06F 9/32 (2013.01); G06F 9/345 (2013.01); G06F 9/3802 (2013.01); G06F 9/3818 (2013.01); G06F 9/383 (2013.01); G06F 9/3836 (2013.01); G06F 9/3851 (2013.01); G06F 9/3856 (2023.08); G06F 9/3867 (2013.01); G06F 9/3887 (2013.01); G06F 9/48 (2013.01); G06F 11/00 (2013.01); G06F 11/1048 (2013.01); G06F 12/0862 (2013.01); G06F 12/0875 (2013.01); G06F 12/0897 (2013.01); G06F 12/1009 (2013.01); G06F 17/16 (2013.01); H03H 17/0664 (2013.01); G06F 9/30018 (2013.01); G06F 9/325 (2013.01); G06F 9/381 (2013.01); G06F 9/3822 (2013.01); G06F 11/10 (2013.01); G06F 15/7807 (2013.01); G06F 15/781 (2013.01); G06F 2212/452 (2013.01); G06F 2212/60 (2013.01); G06F 2212/602 (2013.01); G06F 2212/68 (2013.01)] | 20 Claims |
1. A processing device comprising:
a register file that includes a set of registers each configured to store a respective vector that includes a respective set of elements; and
a permutation circuit coupled to the register file, the permutation circuit including a control input configured to receive control values including a first control value, wherein the permutation circuit is configured to, based on the control values and an instruction that specifies a first register and a second register of the set of registers:
receive a first vector from the first register and a second vector from the second register;
remove every other element of the first vector to produce a set of remaining elements of the first vector;
remove every other element of the second vector to produce a set of remaining elements of the second vector;
provide a combined vector that includes the set of remaining elements of the first vector and the set of remaining elements of the second vector; and
perform a permutation operation on the combined vector based on the first control value to produce an output vector, in which the permutation circuit provides each element of a set of elements of the output vector based on a respective control value portion of the first control value for that element of the set of elements of the output vector.
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