US 12,105,633 B2
Electronic device and method for accelerating memory access
Qunyi Yang, Beijing (CN); Yang Jiao, Beijing (CN); Jin Xiang, Xi'an (CN); Tingli Cui, Xi'an (CN); and Xinglin Gui, Xi'an (CN)
Assigned to SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD., Shanghai (CN)
Filed by Shanghai Zhaoxin Semiconductor Co., Ltd., Shanghai (CN)
Filed on Oct. 19, 2022, as Appl. No. 18/047,791.
Prior Publication US 2023/0128405 A1, Apr. 27, 2023
Int. Cl. G06F 12/0862 (2016.01); G06F 12/0882 (2016.01)
CPC G06F 12/0882 (2013.01) [G06F 12/0862 (2013.01); G06F 2212/7201 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An electronic device, comprising:
a memory, comprising multiple memory pages;
an integrated circuit, converting multiple virtual addresses into multiple physical addresses in sequence; wherein the integrated circuit comprises:
an address remapping unit, prefetching a first physical address corresponding to a first virtual address if a second virtual address exceeds a preset offset, wherein the first virtual address is in a different memory page from the second virtual address, the second virtual address is currently processed, the multiple virtual addresses include the first and second virtual addresses;
wherein the preset offset is set according to latency of reading data from the memory.