US 12,105,628 B2
Apparatus and method for managing cache memory including cache lines with variable cache line configuration
Hyun-Mi Kim, Daejeon (KR)
Assigned to ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, Daejeon (KR)
Filed by ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, Daejeon (KR)
Filed on Oct. 19, 2022, as Appl. No. 17/969,270.
Claims priority of application No. 10-2021-0139512 (KR), filed on Oct. 19, 2021; and application No. 10-2022-0071414 (KR), filed on Jun. 13, 2022.
Prior Publication US 2023/0124538 A1, Apr. 20, 2023
Int. Cl. G06F 12/0802 (2016.01)
CPC G06F 12/0802 (2013.01) [G06F 2212/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus for managing cache memory, comprising:
one or more processors; and
executable memory for storing at least one program executed by the one or more processors,
wherein the at least one program is configured to:
read an s1-tag and an s2-tag of cache memory upon receiving an access request address for reading data in response to a request to access the cache memory, a memory of the s1-tag comprising address information identifying a cache line set and status information indicating one of a plurality of different configurable cache line lengths for one or more cache lines of the identified cache line set,
check whether the access request address matches a value of the s1-tag and a value of the s2-tag, and
read the data from data memory when the access request address matches all of the value of the s1-tag and the value of the s2-tag.