a memory device including a control circuit and a memory cell array that includes a plurality of memory cells disposed at intersections between a plurality of word lines and a plurality of bit lines; and

a memory controller configured to control the memory device and including an error correction code (ECC) circuit that is configured to perform an ECC encoding on write data and an ECC decoding on read data,

wherein the ECC circuit is configured to perform the ECC encoding on the write data to generate a codeword including a first sector and a second sector, and to provide the codeword to the memory device,

wherein the control circuit is configured to perform an ECC interleaving operation on the codeword such that the first sector is written to a first portion of the memory cell array and the second sector is written to a second portion of the memory cell array,

wherein the first portion of the memory cell array has a first bit error rate (BER) and the second portion of the memory cell array has a second bit error rate (BER) that is lower than the first BER,

wherein the memory device is a resistive random access memory (RRAM), a magnetoresistive random access memory (MRAM) or a phase-change random access memory (PRAM),

wherein the plurality of memory cells are resistive type memory cells,

wherein each of the plurality of memory cells includes a variable resistor including an upper electrode, a lower electrode and a dielectric between the upper electrode and the lower electrode,

wherein the memory cell array includes a plurality of memory tiles including a first tile and a second tile, and

wherein the first portion of the memory cell array includes opposite edge portions of the first tile and the second tile, and the second portion of the memory cell array includes portions of the first tile and the second tile respectively between the opposite edge portions of the first tile and the second tile.