| CPC G06F 1/3268 (2013.01) [G06F 1/324 (2013.01); G06F 1/08 (2013.01); G06F 1/3203 (2013.01); G06F 1/3221 (2013.01); G06F 1/3225 (2013.01); G06F 1/3275 (2013.01); G06F 3/0625 (2013.01); G06F 3/0656 (2013.01); G06F 9/546 (2013.01); G06F 11/3409 (2013.01)] | 17 Claims |
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1. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller comprises a processor programmed to:
identify a bottleneck in one or more hardware (HW) modules of a plurality of HW modules, wherein each HW module of the plurality of HW modules operates at a clock frequency, and wherein the clock frequency is dynamic for each HW module;
change the clock frequency of at least one HW module of the plurality of HW modules, wherein changing the clock frequency comprises:
increasing the clock frequency of a first HW module of the plurality of HW modules; and
setting the clock frequency of a second HW module of the plurality of HW modules to match the changed clock frequency of the first HW module, wherein the second HW module is a sub-module of the first HW module; and
monitor the plurality of HW modules for bottleneck issues.
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