US 12,105,553 B2
Synchronizing systems on a chip using a shared clock
Samuel Ahn, Marina Del Rey, CA (US); Jason Heger, Louisville, CO (US); and Dmitry Ryuma, Sherman Oaks, CA (US)
Assigned to Snap Inc., Santa Monica, CA (US)
Filed by Snap Inc., Santa Monica, CA (US)
Filed on Aug. 22, 2023, as Appl. No. 18/236,732.
Application 18/236,732 is a continuation of application No. 17/495,311, filed on Oct. 6, 2021, granted, now 11,775,005, issued on Oct. 3, 2023.
Prior Publication US 2023/0393609 A1, Dec. 7, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/12 (2006.01); G06F 1/04 (2006.01); G06F 1/14 (2006.01); G06F 1/16 (2006.01); G06F 3/01 (2006.01); G06F 13/42 (2006.01); G06F 15/173 (2006.01)
CPC G06F 1/12 (2013.01) [G06F 1/04 (2013.01); G06F 1/14 (2013.01); G06F 1/163 (2013.01); G06F 3/011 (2013.01); G06F 13/4221 (2013.01); G06F 15/17325 (2013.01); G06F 2213/0026 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of synchronizing first and second systems-on-chip (SoCs) of an electronic eyewear device, the first and second SoCs having independent time bases, the method comprising:
a first clock generator of the first SoC generating a common clock;
simultaneously applying a reset pulse to the first SoC and the second SoC;
simultaneously applying the common clock to a first counter of the first SoC to generate a first counter value from counted clock edges of the common clock and to a second counter of the second SoC to generate a second counter value from counted clock edges of the common clock, wherein the first counter and the second counter have independent time bases;
comparing the first counter value and the second counter value;
when a difference between the first counter value and the second counter value is identified, adjusting a counter value of at least one of the first counter or the second counter to cause the first counter value of the first counter and the second counter value of the second counter to match each other; and
after the adjusting, using the first counter value of the first counter to synchronize to a clock output by the first clock generator of the first SoC and the second counter value of the second counter to synchronize to a clock output by a second clock generator of the second SoC so as to synchronize the clocks output by the first clock generator and the second clock generator to each other.