US 12,105,550 B2
Interrupt handling method and apparatus for slow peripherals
Maneesh Soni, Bangalore (IN); Rajeev Suvarna, Bangalore (IN); and Nikunj Khare, Bangalore (IN)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Aug. 18, 2020, as Appl. No. 16/995,852.
Application 16/995,852 is a continuation of application No. 15/420,267, filed on Jan. 31, 2017, granted, now 10,788,853.
Prior Publication US 2020/0379505 A1, Dec. 3, 2020
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/12 (2006.01); G06F 13/24 (2006.01)
CPC G06F 1/12 (2013.01) [G06F 13/24 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a first flip-flop configured to receive a first signal, and to receive a first clock signal;
a second flip-flop coupled to the first flip-flop and configured to receive a logic high signal that does not subsequently transition to a logic low signal, the second flip-flop configured to receive a second signal from the first flip-flop and to provide a third signal; and
a third flip-flop configured to receive an acknowledgment signal, the third flip-flop configured to receive a second clock signal, and the third flip-flop configured to provide a fourth signal to the second flip-flop in response to the acknowledgment signal.