US 12,105,490 B2
Isolation of protection functions in electrical power systems
Sreenivas Dingari, Chester Springs, PA (US); Angelo D'Aversa, Ambler, PA (US); Veselin Skendzic, Schwenksville, PA (US); Chandrasekaran Swaminathan, Orefield, PA (US); and Greg Rzepka, Pullman, WA (US)
Assigned to Schweitzer Engineering Laboratories, Inc., Pullman, WA (US)
Filed by Schweitzer Engineering Laboratories, Inc., Pullman, WA (US)
Filed on Oct. 4, 2021, as Appl. No. 17/492,908.
Prior Publication US 2023/0105068 A1, Apr. 6, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G05B 19/042 (2006.01); G06F 3/06 (2006.01); H02H 1/00 (2006.01)
CPC G05B 19/042 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0646 (2013.01); G06F 3/0673 (2013.01); G05B 2219/24215 (2013.01); G05B 2219/2639 (2013.01); H02H 1/0092 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An intelligent electronic device (IED) for use in an electrical power system, the IED comprising:
a processing subsystem comprising a processor;
a memory subsystem comprising a first memory section and a second memory section, the first memory section including a first set of code to provide at least one protection function relating to the electrical power system, the second memory section including a second set of code to provide at least one additional function relating to the electrical power system that is distinct from the at least one protection function provided by the first set of code;
a memory management subsystem in communication with the processing subsystem to:
in a first operational mode, enable memory access between the processor and the first memory section and the second memory section; and
in a second operational mode, prioritize memory access between the processor and the first memory section;
a protection subsystem comprising the processor and the first memory section to enable use of the at least one protection function with at least a portion of the electrical power system;
wherein the memory management subsystem comprises a processor interrupt feature, the processor interrupt feature to cease the at least one additional function from execution on the processor while the at least one protection function is permitted to execute on the processor.