a substrate;

a plurality of signal lines disposed on the substrate;

a plurality of conductive bumps disposed on a portion of the substrate located in the bonding region, a conductive bump being connected to at least one signal line; and

an insulating layer covering the plurality of signal lines and located between every two adjacent conductive bumps; wherein

the conductive bump includes a conductive metal layer, the conductive bump includes a conductive metal layer, a distance from a surface of the conductive metal layer away from the substrate to the substrate is substantially equal to a distance from a surface of the insulating layer away from the substrate to the substrate; the conductive bump further includes an electrode layer disposed on the surface of the conductive metal layer away from the substrate; and a surface of the electrode layer away from the substrate is parallel to a plane where the substrate is located;

the array substrate further comprising a plurality of thin film transistors disposed on the substrate, a thin film transistor including a gate, a source, and a drain; wherein

the gate and the signal lines are disposed in a same layer, the insulating layer is located on a side of the gate away from the substrate, and the source and the drain are located on a side of the insulating layer away from the substrate;

the conductive metal layer is disposed in a same layer as the source and the drain; and

an orthogonal projection of the conductive metal layer on the substrate is located within an orthogonal projection of a signal line connected to the conductive metal layer on the substrate.