a first plurality of signal analysis circuits configured to analyze signals generated by a plurality of DUTs;

a second plurality of signal processing units configured to process the signals analyzed by the first plurality of signal analysis circuits; and

a switch array electrically coupled between the first plurality of signal analysis circuits and the second plurality of signal processing units, said switch array configured to electrically connect selected ones of the first plurality of signal analysis circuits with corresponding ones of the second plurality of signal processing units; and

a switch controller configured to detect electrical connections between the DUTs and the first plurality of signal analysis circuits and selectively disable a switch within the switch array, which extends between a signal processing unit within the second plurality thereof and an inactive one of the first plurality of signal analysis circuits, which is electrically disconnected from a DUT;

wherein the switch array is responsive to signals generated by the switch controller; and

wherein the number of signal processing units within the second plurality is less than a maximum number of DUTs that can be connected to the first plurality of signal analysis circuits when the tester is testing a plurality of the DUTs, and the switch controller is configured to always maximize the number of DUTs that can be simultaneously tested at a number equivalent to the total number of signal processing units within the second plurality thereof whenever the number of untested DUTs within the plurality thereof, which are electrically connected to corresponding ones of the signal analysis circuits, is greater than the number of signal processing units within the second plurality thereof.