specifying a first pin assignment with N input pins and R merged input pins, N and R being integers, N corresponding to a number of input pins for carrying scan-in chain test data, and R corresponding to a number of input pins for carrying a merged expected test result and a masking instruction signal;

specifying a second pin assignment with N input pins and M output pins, M being an integer and corresponding to a number of output pins for carrying scan-out chain test data;

generating an N by M codec;

integrating the N by M codec and inserting scan chains, wherein device registers are stitched into multiple scan chains and coupled between a compression circuit and a decompression circuit;

decoding output signals from the merged expected test result and the masking instruction signal received from the R merged input pins;

receiving the scan-in chain test data; and

comparing the decoded output signals comprising an expected test result with a test result chain.