US 12,105,137 B2
Virtual quality control interpolation and process feedback in the production of memory devices
Yusuke Ikawa, Yokohama (JP); Tsuyoshi Sendoda, Kuwana (JP); Kei Samura, Yokohama (JP); and Masaaki Higashitani, Cupertino, CA (US)
Assigned to SanDisk Technologies LLC, Addison, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Jun. 28, 2021, as Appl. No. 17/360,573.
Prior Publication US 2022/0413036 A1, Dec. 29, 2022
Int. Cl. G01R 31/27 (2006.01); G01R 31/317 (2006.01); G01R 31/3181 (2006.01); G01R 31/3183 (2006.01); G06N 3/063 (2023.01)
CPC G01R 31/275 (2013.01) [G01R 31/31707 (2013.01); G01R 31/31813 (2013.01); G01R 31/31835 (2013.01); G06N 3/063 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
manufacturing a first plurality of an integrated circuit according to a first set of processing parameter values;
selecting a subset of the first plurality of the integrated circuit during manufacturing as first test samples;
performing one or more first tests on the first test samples;
performing one or more second tests on the first plurality of the integrated circuit subsequent to completing the manufacturing of the first plurality of the integrated circuit;
performing a machine learning process to determine a correlation between results of the one or more first tests and results of the one or more second tests;
subsequent to performing the machine learning process, manufacturing a second plurality of the integrated circuit according to the first set of processing parameter values;
performing the one or more second tests on the second plurality of the integrated circuit; and
interpolating results of the one or more first tests for members of the second plurality of the integrated circuit from the correlation and results of the one or more second tests on the second plurality of the integrated circuit.