US 12,105,123 B2
Zero-crossing detection circuit
Satoru Nate, Kyoto (JP); Akinobu Sawada, Kyoto (JP); and Natsuki Yamamoto, Kyoto (JP)
Assigned to Rohm Co., Ltd., Kyoto (JP)
Filed by Rohm Co., Ltd., Kyoto (JP)
Filed on Jul. 7, 2023, as Appl. No. 18/348,701.
Application 18/348,701 is a continuation of application No. 17/499,138, filed on Oct. 12, 2021, granted, now 11,733,275.
Application 17/499,138 is a continuation of application No. 16/634,296, granted, now 11,181,562, issued on Nov. 23, 2021, previously published as PCT/JP2018/027792, filed on Jul. 25, 2018.
Claims priority of application No. 2017148233 (JP), filed on Jul. 31, 2017; application No. 2017182109 (JP), filed on Sep. 22, 2017; and application No. 2017182111 (JP), filed on Sep. 22, 2017.
Prior Publication US 2023/0358792 A1, Nov. 9, 2023
Int. Cl. G01R 19/175 (2006.01); H02M 1/08 (2006.01); H03K 5/1536 (2006.01)
CPC G01R 19/175 (2013.01) [H02M 1/083 (2013.01); H03K 5/1536 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A zero-crossing detection circuit comprising:
a logic unit configured to estimate a zero cross of an AC signal in accordance with at least one of a first monitoring target signal and a second monitoring target signal, respectively input through diodes from a first node and a second node between which the AC signal is applied, so as to generate a zero-crossing detection signal, and
an input stop detection unit configured to compare the first monitoring target signal with the second monitoring target signal after giving an offset to one of them so as to generate an input stop detection signal,
wherein the logic unit is configured to fix a logic level of the zero-crossing detection signal in accordance with the input stop detection signal.