US 12,104,950 B2
Optical receiver
Hiroshi Hara, Osaka (JP); and Kosuke Okawa, Osaka (JP)
Assigned to SUMITOMO ELECTRIC INDUSTRIES, LTD., Osaka (JP)
Appl. No. 18/259,598
Filed by SUMITOMO ELECTRIC INDUSTRIES, LTD., Osaka (JP)
PCT Filed Jan. 14, 2022, PCT No. PCT/JP2022/001119
§ 371(c)(1), (2) Date Jun. 28, 2023,
PCT Pub. No. WO2022/163391, PCT Pub. Date Aug. 4, 2022.
Claims priority of application No. 2021-010186 (JP), filed on Jan. 26, 2021.
Prior Publication US 2024/0053196 A1, Feb. 15, 2024
Int. Cl. G01J 1/44 (2006.01); H03F 3/45 (2006.01); H04B 10/60 (2013.01); H04B 10/67 (2013.01); H05K 1/02 (2006.01); H05K 1/18 (2006.01)
CPC G01J 1/44 (2013.01) [H03F 3/45475 (2013.01); H04B 10/60 (2013.01); H04B 10/67 (2013.01); H05K 1/0231 (2013.01); H05K 1/181 (2013.01); H05K 2201/10121 (2013.01)] 7 Claims
OG exemplary drawing
 
1. An optical receiver comprising:
a light-receiving element having an anode pad connected to an anode electrode through an anode wiring pattern and a first cathode pad and a second cathode pad connected to a cathode electrode through a cathode wiring pattern and arranged at positions interposing the anode pad; and
a transimpedance amplifier including a cathode wiring layer supplying a cathode potential to the cathode pad of the light-receiving element, an insulating layer having the cathode wiring layer therein, a first pad provided on the insulating layer and connected to the anode pad of the light-receiving element, and a second pad connected to the first cathode pad of the light-receiving element and a third pad connected to the second cathode pad of the light-receiving element provided on the insulating layer, connected to the cathode wiring layer through a first via, and arranged at positions interposing the first pad,
wherein the light-receiving element is connected to the anode pad mounted on the transimpedance amplifier and connected through the anode electrode and the anode wiring pattern provided on a surface facing the transimpedance amplifier and the first cathode pad and the second cathode pad connected through the cathode electrode and the cathode wiring pattern and arranged at positions interposing the anode pad,
wherein the transimpedance amplifier further includes a ground layer connected to a reference potential, and
wherein the ground layer of the transimpedance amplifier is connected to the cathode wiring layer of the transimpedance amplifier through a capacitor,
further comprising a back surface ground provided on a back surface of the transimpedance amplifier and connected to a reference potential,
wherein the ground layer of the transimpedance amplifier is provided on a back surface side of the cathode wiring layer and connected to the back surface ground through a TSV through silicon via) or a DSV (deep silicon via).