an integrated circuit having a first terminal to which a master/slave switching signal is input at a start of data acquisition, an A/D converter for converting analog input data to digital data, and an output terminal for outputting the digital data, the integrated circuit operating in either a master mode or a slave mode according to the master/slave switching signal; and

an information processor having a switching setting part that generates the mater/slave switching signal, a second terminal connected to the first terminal and for outputting the master/slave switching signal, and an input terminal connected to the output terminal and for receiving the digital data, the switching setting part configuring the information processor to operate in the master mode when the integrated circuit operates in the slave mode, and to operate in the slave mode when the integrated circuit operates in the master mode,

wherein the integrated circuit is configured to output a synchronizing signal to the information processor to allow the information processor to acquire the digital data and configured to output the digital data from the output terminal when operating in the master mode according to the master/slave switching signal supplied from the information processor,

wherein the information processor is configured to generate a system clock and correct a timing of the system clock using the synchronizing signal supplied from the integrated circuit when the information processor is operating in the slave mode, and

wherein the information processor is configured to reduce a clock frequency when the information processor is operating in the slave mode compared to when the information processor is operating in the master mode.