US 11,778,837 B2
Memory with optimized resistive layers
Lei Wei, Boise, ID (US); Pengyuan Zheng, Boise, ID (US); Kevin Lee Baker, Boise, ID (US); Efe Sinan Ege, Boise, ID (US); Adam Thomas Barton, Boise, ID (US); and Rajasekhar Venigalla, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 22, 2022, as Appl. No. 17/846,731.
Application 17/846,731 is a division of application No. 16/941,885, filed on Jul. 29, 2020, granted, now 11,380,732.
Prior Publication US 2022/0406847 A1, Dec. 22, 2022
Int. Cl. H01L 27/24 (2006.01); H01L 45/00 (2006.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10B 63/84 (2023.02) [H10N 70/063 (2023.02); H10N 70/231 (2023.02); H10N 70/826 (2023.02); H10N 70/841 (2023.02); H10N 70/8616 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
depositing a first resistive material on a plurality of memory stacks, each of the memory stacks including a layered assembly of electrode materials and a memory material;
depositing, on the plurality of memory stacks over the first resistive material, a first conductive material;
removing an area of the plurality of memory stacks to form a gap in the first resistive material, the first conductive material, and one or more memory stacks of the plurality of memory stacks;
depositing a conductive material to form a conductive via in the gap;
depositing, over the first conductive material and the conductive via, a second resistive material; and
depositing, on the plurality of memory stacks over the second resistive material and on the conductive via over the second resistive material, a second conductive material.