US 11,778,825 B2
Method of fabricating a vertical semiconductor device
Bongyong Lee, Suwon-si (KR); Taehun Kim, Gwacheon-si (KR); Minkyung Bae, Hwaseong-si (KR); Myunghun Woo, Suwon-si (KR); and Doohee Hwang, Uiwang-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 24, 2022, as Appl. No. 17/702,967.
Application 17/702,967 is a continuation of application No. 16/838,106, filed on Apr. 2, 2020, granted, now 11,315,946.
Claims priority of application No. 10-2019-0068800 (KR), filed on Jun. 11, 2019.
Prior Publication US 2022/0216233 A1, Jul. 7, 2022
Int. Cl. H10B 43/27 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating a vertical semiconductor device, the method comprising:
forming a lower sacrificial layer pattern on a substrate;
forming a support layer on the lower sacrificial layer pattern;
alternately stacking a sacrificial layer and an insulating layer on the support layer;
forming a channel hole penetrating the sacrificial layer, the insulating layer, the support layer, and the lower sacrificial layer pattern;
partially removing an exposed sidewall of the support layer in the channel hole;
forming an information storage material layer and a channel pattern in the channel hole so that the information storage material layer and the channel pattern fill a space formed by partially removing the exposed sidewall of the support layer in the channel hole;
replacing the lower sacrificial layer pattern with a common source semiconductor layer; and
replacing the sacrificial layer with gates.