CPC H10B 43/27 (2023.02) [H01L 21/76254 (2013.01); H01L 24/08 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H10B 41/27 (2023.02); H01L 21/0245 (2013.01); H01L 21/02513 (2013.01); H01L 21/02538 (2013.01); H01L 21/02595 (2013.01); H01L 21/02598 (2013.01); H01L 2224/08145 (2013.01)] | 20 Claims |
1. A method of forming a three-dimensional memory device, comprising:
providing a first assembly including a transfer substrate, a single-crystalline germanium-containing layer, and a first silicon oxide component layer;
providing a second assembly including a substrate material layer and a second silicon oxide component layer;
bonding the first silicon oxide component layer to the second silicon oxide component layer to form a silicon oxide layer;
detaching the transfer substrate from an assembly including, from bottom to top, the substrate material layer, the silicon oxide layer, and the single-crystalline germanium-containing layer;
growing a single-crystalline III-V compound semiconductor layer on the single-crystalline germanium-containing layer;
forming an alternating stack of insulating layers and spacer material layers over the single-crystalline III-V compound semiconductor layer, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers;
forming memory openings through the alternating stack; and
forming memory opening fill structures in the memory openings, wherein each memory opening fill structure comprises a memory film and a vertical semiconductor channel having a bottom end that is electrically connected to the single-crystalline III-V compound semiconductor layer.
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