CPC H04W 28/26 (2013.01) [H04L 5/0051 (2013.01); H04L 5/10 (2013.01); H04W 4/40 (2018.02); H04W 52/52 (2013.01); H04W 72/0446 (2013.01); H04W 92/18 (2013.01)] | 20 Claims |
1. An apparatus for wireless communication at a receiving device, comprising:
one or more memories; and
at least one processor coupled to the one or more memories and configured to:
perform automatic gain control during a first symbol of a subframe, wherein the automatic gain control converges prior to an end of the first symbol of the subframe;
receive a pilot signal or a demodulation reference signal (DM-RS) during the first symbol based on the automatic gain control converging prior to the end of the first symbol of the subframe, wherein the pilot signal or the DM-RS spans an entire first symbol of the subframe;
receive at least a portion of a sidelink transmission during the subframe; and
decode the sidelink transmission to determine complex valued symbols that are mapped in sequence to physical resource blocks of the sidelink transmission, wherein the complex valued symbols are not mapped to resource elements in the first symbol of the subframe.
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