US 11,777,485 B2
Bypass circuitry to improve switching speed
Ravindranath D. Shrivastava, San Diego, CA (US); Simon Willard, Irvine, CA (US); and Peter Bacon, New Hampshire, CT (US)
Assigned to PSEMI CORPORATION, San Diego, CA (US)
Filed by pSemi Corporation, San Diego, CA (US)
Filed on Apr. 26, 2022, as Appl. No. 17/660,725.
Application 17/660,725 is a continuation of application No. 17/202,003, filed on Mar. 15, 2021, granted, now 11,329,642.
Prior Publication US 2022/0321113 A1, Oct. 6, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 17/04 (2006.01); H03K 17/0412 (2006.01)
CPC H03K 17/04123 (2013.01) 19 Claims
OG exemplary drawing
 
1. A radio frequency (RF) field effect transistor (FET) switch stack comprising:
FET transistors arranged in a stacked configuration;
one or more first drain-source resistors, each first drain-source resistor coupled across drain-source terminals of a corresponding FET transistor of the FET transistors;
one or more drain-source bypass switches, each drain-source bypass switch coupled across corresponding one or more first drain-source resistors; and
a switching control block configured to control the drain-source bypass switches, the switching control block comprising one or more FET control switches configured to be in a control switch OFF state when the FET transistors are in a stack OFF state or a stack ON state and to be in a control switch ON state when the FET transistors are transitioning from the stack ON state to the stack OFF state.