US 11,777,026 B2
Power semiconductor device having low-k dielectric gaps between adjacent metal contacts
Anita Brazzale, Villach (AT); Robert Haase, San Pedro, CA (US); Sylvain Leomant, Poertschach am Woerthersee (AT); and Harsh Naik, El Segundo, CA (US)
Assigned to Infineon Technologies Austria AG, Villach (AT)
Filed by Infineon Technologies Austria AG, Villach (AT)
Filed on Jun. 21, 2021, as Appl. No. 17/352,954.
Prior Publication US 2022/0406930 A1, Dec. 22, 2022
Int. Cl. H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/45 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7813 (2013.01) [H01L 29/0696 (2013.01); H01L 29/404 (2013.01); H01L 29/45 (2013.01); H01L 29/495 (2013.01); H01L 29/4916 (2013.01); H01L 29/66734 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a Si substrate having a first main surface;
a plurality of gate trenches extending from the first main surface into the Si substrate;
a semiconductor mesa between adjacent gate trenches;
a first interlayer dielectric on the first main surface;
a plurality of first metal contacts extending through the first interlayer dielectric and contacting gate electrodes disposed in the gate trenches;
a plurality of second metal contacts extending through the first interlayer dielectric and contacting the semiconductor mesas; and
an air gap or a dielectric material having a lower dielectric constant than the first interlayer dielectric between adjacent first and second metal contacts.