US 11,776,994 B2
SiC MOSFET with reduced channel length and high Vth
David Sheridan, Greensboro, NC (US); Arash Salemi, Cary, NC (US); and Madhur Bobde, Sunnyvale, CA (US)
Assigned to Alpha and Omega Semiconductor International LP, Toronto (CA)
Filed by Alpha and Omega Semiconductor International LP, Toronto (CA)
Filed on Feb. 16, 2021, as Appl. No. 17/177,045.
Prior Publication US 2022/0262896 A1, Aug. 18, 2022
Int. Cl. H01L 21/04 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01)
CPC H01L 29/063 (2013.01) [H01L 21/0465 (2013.01); H01L 29/1095 (2013.01); H01L 29/1608 (2013.01); H01L 29/66068 (2013.01); H01L 29/7802 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A silicon carbide MOSFET comprising:
a substrate heavily doped with a first conductivity type;
an epitaxial layer lightly doped with the first conductivity type having a junction field effect transistor (JFET) region of the first conductivity type;
a body region doped with a second conductivity type formed in the epitaxial layer wherein the second conductivity type is opposite the first conductivity type;
an accumulation mode region doped with the first conductivity type formed in the body region and an inversion mode region of the second conductivity type formed in the body region, wherein the accumulation mode region is located between the JFET region and the inversion mode region; and
a source region with the first conductivity type doped from a surface of the epitaxial layer to a depth deeper than a bottom of the inversion mode region.