US 11,776,982 B2
Image sensor chip
Minho Jang, Suwon-si (KR); Doowon Kwon, Seongnam-si (KR); Dongchan Kim, Seongnam-si (KR); Bokwon Kim, Suwon-si (KR); Kyungrae Byun, Seoul (KR); Jungchak Ahn, Yongin-si (KR); and Hyunyoung Yeo, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Dec. 28, 2020, as Appl. No. 17/134,699.
Claims priority of application No. 10-2020-0054319 (KR), filed on May 7, 2020.
Prior Publication US 2021/0351220 A1, Nov. 11, 2021
Int. Cl. H01L 27/146 (2006.01); H01L 25/065 (2023.01)
CPC H01L 27/14636 (2013.01) [H01L 25/0657 (2013.01); H01L 27/14621 (2013.01); H01L 27/14623 (2013.01); H01L 27/14627 (2013.01); H01L 2225/06541 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An image sensor chip comprising:
a lower chip;
an upper chip stacked on the lower chip and including a first photoelectric element;
a first via hole penetrating through the upper chip and penetrating through at least a portion of the lower chip; and
a first conductive connection layer in the first via hole,
wherein the lower chip includes a lower substrate having a first surface and a second surface opposing each other, a lower interconnection structure including a first lower pad on the first surface of the lower substrate, and a lower insulating structure covering the lower interconnection structure on the first surface of the lower substrate,
the upper chip further includes an upper substrate having a third surface and a fourth surface opposing each other, an upper element and an upper interconnection structure below the third surface of the upper substrate, and an upper insulating structure covering the upper element and the upper interconnection structure below the third surface of the upper substrate,
a lower surface of the upper insulating structure contacts an upper surface of the lower insulating structure,
the third surface of the upper substrate and the first surface of the lower substrate face each other,
the upper interconnection structure includes an upper circuit interconnection structure and an upper interconnection line structure,
the upper circuit interconnection structure includes a circuit contact plug electrically connected to the upper element, and a multilayer circuit interconnection line electrically connected to the circuit contact plug,
the upper interconnection line structure includes a connection contact plug and a multilayer interconnection line below and contacting the connection contact plug,
the first conductive connection layer is in contact with the connection contact plug in the upper chip and the first lower pad in the lower chip and is spaced apart from the multilayer interconnection line in the upper chip,
the first conductive connection layer is configured to electrically connect the connection contact plug and the first lower pad to each other,
the upper element includes a transistor including a source/drain region, a gate dielectric layer and a gate electrode,
at least a portion of the gate electrode is at the same level as a portion of the connection contact plug,
the gate electrode has an upper surface contacting the gate dielectric layer and a lower surface opposing the upper surface of the gate electrode, and
a lower surface of the connection contact plug is at a lower level than the lower surface of the gate electrode.