US 11,776,957 B2
Gate cut with integrated etch stop layer
Marc A. Bergendahl, Troy, NY (US); Andrew M. Greene, Albany, NY (US); and Rajasekhar Venigalla, Hopewell Junction, NY (US)
Assigned to TESSERA LLC, San Jose, CA (US)
Filed by TESSERA LLC, San Jose, CA (US)
Filed on Dec. 7, 2022, as Appl. No. 18/76,755.
Application 18/076,755 is a continuation of application No. 17/221,401, filed on Apr. 2, 2021, granted, now 11,552,077.
Application 17/221,401 is a continuation of application No. 16/738,569, filed on Jan. 9, 2020, granted, now 10,998,314, issued on May 4, 2021.
Application 16/738,569 is a continuation of application No. 16/054,394, filed on Aug. 3, 2018, granted, now 10,580,773, issued on Mar. 3, 2020.
Application 16/054,394 is a continuation of application No. 15/258,513, filed on Sep. 7, 2016, granted, now 10,083,961, issued on Sep. 25, 2018.
Prior Publication US 2023/0282641 A1, Sep. 7, 2023
Int. Cl. H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 21/3213 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 23/62 (2006.01); H01L 21/02 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0886 (2013.01) [H01L 21/02181 (2013.01); H01L 21/31144 (2013.01); H01L 21/32133 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823468 (2013.01); H01L 21/823475 (2013.01); H01L 21/823821 (2013.01); H01L 23/5286 (2013.01); H01L 23/5329 (2013.01); H01L 23/62 (2013.01); H01L 27/0924 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor structure, the method comprising:
forming a gate structure on first and second active regions of the semiconductor structure;
removing a portion of the gate structure to define a first gate structure on the first active region and a second gate structure on the second active region, wherein the first and second gate structures are in-line with one another and spaced apart by a gate cut trench;
forming a first etch stop layer in the gate cut trench;
forming a first dielectric material on the first etch stop layer in a lower portion of the gate cut trench;
forming a second etch stop layer on an upper surface of the first dielectric material; and
forming a second dielectric material on the second etch stop layer in an upper portion of the gate cut trench.