US 11,776,869 B2
Package with a highly conductive layer deposited on die using throughput additive deposition prior to TIM1 dispense
Feras Eid, Chandler, AZ (US); Johanna M. Swan, Scottsdale, AZ (US); Sergio Chan Arguedas, Chandler, AZ (US); and John J. Beatty, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 11, 2022, as Appl. No. 17/718,031.
Application 17/718,031 is a continuation of application No. 16/639,545, granted, now 11,328,978, previously published as PCT/US2017/054676, filed on Sep. 30, 2017.
Prior Publication US 2022/0238411 A1, Jul. 28, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/367 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/10 (2006.01); H01L 49/02 (2006.01); H01L 23/42 (2006.01)
CPC H01L 23/3675 (2013.01) [H01L 21/4882 (2013.01); H01L 28/40 (2013.01); H01L 23/10 (2013.01); H01L 23/42 (2013.01); H01L 24/30 (2013.01); H01L 24/32 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device package, comprising:
one or more dies disposed on a substrate;
one or more conductive layers disposed on the one or more dies, wherein the one or more conductive layers comprises a first conductive layer laterally adjacent to a second conductive layer on one of the one or more dies, the second conductive layer different than the first conductive layer; and
a lid with one or more legs on an outer periphery of the lid, a top surface, and a bottom surface that is opposite from the top surface, wherein the one or more legs of the lid are attached to the substrate with a sealant, and wherein the bottom surface of the lid is disposed over the one or more conductive layers and the one or more dies on the substrate.