US 11,776,619 B2
Techniques to couple high bandwidth memory device on silicon substrate and package substrate
Chong J. Zhao, West Linn, OR (US); James A. McCall, Portland, OR (US); Shigeki Tomishima, Portland, OR (US); George Vergis, Portland, OR (US); and Kuljit S. Bains, Olympia, WA (US)
Assigned to Tahoe Research, Ltd., Dublin (IE)
Filed by Tahoe Research, Ltd., Dublin (IE)
Filed on Jan. 11, 2023, as Appl. No. 18/153,183.
Application 17/368,732 is a division of application No. 16/737,666, filed on Jan. 8, 2020, granted, now 11,056,179, issued on Jul. 6, 2021.
Application 18/153,183 is a continuation of application No. 17/368,732, filed on Jul. 6, 2021, granted, now 11,557,333, issued on Jan. 17, 2023.
Prior Publication US 2023/0145937 A1, May 11, 2023
Int. Cl. G11C 29/02 (2006.01); G11C 11/4093 (2006.01); G11C 11/4096 (2006.01); G11C 11/408 (2006.01); H10B 12/00 (2023.01)
CPC G11C 11/4093 (2013.01) [G11C 11/408 (2013.01); G11C 11/4096 (2013.01); H10B 12/00 (2023.02); G11C 29/02 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a mode register to indicate a mode of operation for a high bandwidth memory stack device to include a plurality of memory devices stacked above a logic layer; and
circuitry at the logic layer to execute logic, the logic to:
read a value of the mode register; and
cause, based on the value of the mode register, a portion of input/output (I/O) contacts on a bottom side of the logic layer to be inactive and a remaining portion of the I/O contacts to be active, the portion of I/O contacts arranged to receive or transmit I/O signals for one or more data channels to access the plurality of memory devices.