| CPC G11C 7/1015 (2013.01) [G11C 11/1655 (2013.01); G11C 11/1657 (2013.01); G11C 11/1659 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01)] | 19 Claims |
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1. A method, comprising:
providing single port memory with a plurality of different banks having a first bank of bitcells and a second bank of bitcells that is different than the first bank of bitcells;
coupling a plurality of wordlines to the single port memory including coupling a first wordline to each bitcell in the first bank and coupling a second wordline to each bitcell in the second bank;
coupling a plurality of shared bitlines to the single port memory including coupling a plurality of first shared bitlines to each bitcell in the first bank and coupling a plurality of second shared bitlines to each bitcell in the second bank;
coupling a plurality of shared read bitlines to the single port memory including coupling a plurality of first shared read bitlines to the first shared bitlines for each bitcell in the first bank and coupling a plurality of second shared read bitlines to the second shared bitlines for each bitcell in the second bank; and
performing a plurality of memory access operations concurrently in the single port memory including performing a read operation in the first bank using the first wordline and the plurality of first shared read bitlines while performing a write operation in the second bank using the second wordline and the plurality of second shared bitlines, or performing a write operation in the first bank using the first wordline and the plurality of first shared bitlines while performing a read operation in the second bank using the second wordline and the plurality of second read shared bitlines.
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