CPC G11C 7/1009 (2013.01) [G11C 7/06 (2013.01); G11C 7/1012 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 29/42 (2013.01)] | 20 Claims |
1. A method of operating memory cells, comprising:
receiving a previous user data and a new user data;
determining mask register information based at least in part on receiving the previous user data and the new user data;
counting one or more first quantities of a first logic value and one or more second quantities of a second logic value to be written based at least in part on the mask register information and the new user data;
storing a quantity of bits having the first logic value into a first counter and storing a quantity of bits having the second logic value into a second counter;
applying a programming pulse to the memory cells according to the mask register information based at least in part on initiating a write sequence programming sequence using a first write sequence or a second write sequence; and
performing an error correction operation based at least in part on comparing a quantity of programmed memory cells to a threshold quantity of programmed memory cells having the first logic value or the second logic value.
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