CPC G06J 1/02 (2013.01) [G06F 17/16 (2013.01)] | 29 Claims |
1. An accelerator comprising:
a plurality of digital-to-analog converters (DACs) configured to generate a plurality of input analog signals based on a data vector;
an analog processor arranged to perform matrix-vector multiplication and comprising inputs and outputs;
a plurality of n-bit analog-to-digital converters (ADCs) coupled to respective outputs of the analog processor, where n is equal to or less than 16;
a plurality of analog amplifiers, coupled between the plurality of DACs and respective inputs of the analog processor, configured to generate a plurality of amplified input analog signals based on the plurality of input analog signals; and
a controller configured to:
receive a set of parameters representing a matrix;
set a first gain of a first analog amplifier of the plurality of analog amplifiers and a second gain of a second amplifier of the plurality of analog amplifiers, wherein the first gain is different from the second gain;
control the analog processor to generate a plurality of output analog signals based on the plurality of amplified input analog signals and the set of parameters; and
control the plurality of ADCs to digitize the plurality of output analog signals.
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