CPC G06F 30/39 (2020.01) [G06F 30/30 (2020.01); G06F 30/33 (2020.01); G06F 30/3323 (2020.01); G06F 30/367 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); H01L 23/573 (2013.01); G06F 2119/18 (2020.01)] | 22 Claims |
1. A method for generating an integrated circuit (IC) chip design, comprising:
receiving, by a server, a plurality of electrical parameters of a system on chip (SoC) to be designed, wherein the plurality of electrical parameters are received on a data sheet;
receiving a plurality of physical parameters of the SoC on the data sheet;
generating a first design of the SoC according to the plurality of electrical parameters and the plurality of physical parameters;
receiving a plurality of test parameters for testing the first design;
testing, via a design verification tool, the first design by applying the plurality of test parameters to the first design;
receiving a second design of a second SoC;
coupling the second design to the first design to generate a first IC chip design; and
arranging the first IC chip design to be included on a shuttle for fabricating a first IC chip.
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