US 11,775,446 B2
Methods and apparatus to facilitate atomic compare and swap in cache for a coherent level 1 data cache system
Naveen Bhoria, Plano, TX (US); Timothy David Anderson, University Park, TX (US); and Pete Michael Hippleheuser, Murphy, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Sep. 13, 2021, as Appl. No. 17/472,811.
Application 17/472,811 is a continuation of application No. 16/882,272, filed on May 22, 2020, granted, now 11,119,935.
Claims priority of provisional application 62/852,494, filed on May 24, 2019.
Prior Publication US 2021/0406190 A1, Dec. 30, 2021
Int. Cl. G06F 12/0811 (2016.01); G06F 12/02 (2006.01); G06F 12/0897 (2016.01); G06F 12/0888 (2016.01); G06F 12/0891 (2016.01); G06F 9/54 (2006.01); G06F 12/128 (2016.01); G06F 12/0817 (2016.01); G06F 12/0804 (2016.01); G06F 9/30 (2018.01); G11C 7/10 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01); G06F 11/10 (2006.01); G06F 12/0855 (2016.01); G06F 12/12 (2016.01); G06F 12/0806 (2016.01); G06F 12/0815 (2016.01); G06F 12/0853 (2016.01); G06F 13/16 (2006.01); G06F 12/121 (2016.01); G06F 12/0884 (2016.01); G06F 12/0895 (2016.01); G06F 12/0864 (2016.01); G11C 7/22 (2006.01); G11C 5/06 (2006.01); G06F 15/80 (2006.01); G06F 12/0802 (2016.01); G06F 12/126 (2016.01)
CPC G06F 12/0811 (2013.01) [G06F 9/3001 (2013.01); G06F 9/30043 (2013.01); G06F 9/30047 (2013.01); G06F 9/546 (2013.01); G06F 11/1064 (2013.01); G06F 12/0215 (2013.01); G06F 12/0238 (2013.01); G06F 12/0292 (2013.01); G06F 12/082 (2013.01); G06F 12/0802 (2013.01); G06F 12/0804 (2013.01); G06F 12/0806 (2013.01); G06F 12/0815 (2013.01); G06F 12/0853 (2013.01); G06F 12/0855 (2013.01); G06F 12/0864 (2013.01); G06F 12/0884 (2013.01); G06F 12/0888 (2013.01); G06F 12/0891 (2013.01); G06F 12/0895 (2013.01); G06F 12/0897 (2013.01); G06F 12/12 (2013.01); G06F 12/121 (2013.01); G06F 12/126 (2013.01); G06F 12/128 (2013.01); G06F 13/1605 (2013.01); G06F 13/1642 (2013.01); G06F 13/1673 (2013.01); G06F 13/1689 (2013.01); G06F 15/8069 (2013.01); G11C 5/066 (2013.01); G11C 7/10 (2013.01); G11C 7/106 (2013.01); G11C 7/1015 (2013.01); G11C 7/1075 (2013.01); G11C 7/1078 (2013.01); G11C 7/1087 (2013.01); G11C 7/222 (2013.01); G11C 29/42 (2013.01); G11C 29/44 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1041 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/301 (2013.01); G06F 2212/454 (2013.01); G06F 2212/608 (2013.01); G06F 2212/6032 (2013.04); G06F 2212/6042 (2013.01); G06F 2212/62 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit device comprising:
a first cache memory associated with a cache hierarchy and configured to store a first set of data;
a state memory configured to store a state of each unit of data of the first set of data;
a cache controller coupled to the first cache memory and the state memory and configured to couple to a second cache memory associated with the cache hierarchy, wherein the cache controller is configured to:
receive a compare-and-swap operation that specifies a memory address; and
based on the compare-and-swap operation:
determine whether a second set of data associated with the memory address is stored in the first cache memory;
based on the second set of data not being in the first set of data stored in the first cache memory, provide a request for the second set of data from the second cache memory; and
based on the second set of data being in the first set of data stored in the first cache memory:
determine, based on the state memory, a state associated with the second set of data; and
based on the state associated with the second set of data being a shared state, provide the request for the second set of data from the second cache memory.