US 11,775,442 B2
Memory system with a predictable read latency from media with a long write latency
Monish Shantilal Shah, Sammamish, WA (US); and John Grant Bennett, Sammamish, WA (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Jan. 25, 2022, as Appl. No. 17/583,831.
Application 17/583,831 is a continuation of application No. 16/884,217, filed on May 27, 2020, granted, now 11,269,779.
Prior Publication US 2022/0147461 A1, May 12, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/08 (2016.01); G06F 12/0895 (2016.01); G06F 11/10 (2006.01)
CPC G06F 12/0895 (2013.01) [G06F 11/1004 (2013.01); G06F 2212/1024 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for operating a memory system comprising at least one array of N rows of tiles and M columns of tiles, wherein each of N and M is an integer, wherein each of the tiles is configured to store data corresponding to at least one cache line associated with a host, and wherein each of the tiles comprises memory cells, the method comprising:
in response to a write command from a host, initiating writing of a first cache line to a first tile in a first row of the N rows of tiles, a second cache line to a second tile in a second row of the N rows of tiles, a third cache line to a third tile in a third row of the N rows of tiles, and a fourth cache line in a fourth row of the N rows of tiles, and having at least N cache lines to be written in response to the write command from the host; and
in response to a read command from the host, initiating reading of data stored in an entire row of tiles, and haying at least M cache lines to be read in response to the read command from the host.